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Huawei After Sanctions: CIDM, Kirin 9050, and Logic Folding (Pt.2)
Cut off from EUV, Huawei is scaling a different way: folding two chips face to face so signals travel down rather than across. Part 2 explains why that raises clock speed without shrinking transistors, how the design repairs its own defects, and where the real wall lies.
Huawei After Sanctions: CIDM, Kirin 9050, and Logic Folding (Pt.1)
US sanctions bought time, not a lead. Huawei’s CIDM now ships Kirin 9050 with 1.5 µm wafer-to-wafer bonds — about 6× finer than TSMC SoIC. A coarse bond stacks two chips. A fine bond folds one circuit: two wafers, one netlist, one chip.
Notes: The Bottleneck Heuristic — The Memory Supercycle, Power Bottleneck, and Data Center Value Creation (Pt.3)
The memory supercycle is no longer just about HBM. Multi-tier architectures are pulling conventional DRAM and NAND into the same structural shortage, while power and PCB bottlenecks are now compounding the constraint.