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Huawei After Sanctions: CIDM, Kirin 9050, and Logic Folding (Pt.2)
Cut off from EUV, Huawei is scaling a different way: folding two chips face to face so signals travel down rather than across. Part 2 explains why that raises clock speed without shrinking transistors, how the design repairs its own defects, and where the real wall lies.
Notes: The Bottleneck Heuristic — Blackwell's Gauntlet, the ASIC Breakout, and the Optical Chokepoint (Pt.2)
Blackwell’s packaging, cooling, NVL72, and on-chip SFU bottlenecks exposed NVDA’s gauntlet — while Google’s AVGO-designed TPUv7 shattered the ASIC skepticism and the optical chokepoint tightened into 2025’s defining constraint.
SysMoore & Energy (Pt.3.3) - The Nuclear Investment Thesis
A three-decade “nuclear winter” of chronic underinvestment hollowed out the global uranium supply base — creating a structural scarcity shock as AI’s power hunger collides with a mining industry unable to respond at scale.