A fine hybrid bond does not stack two chips. It folds one circuit across two wafers.

Huawei

Huawei After Sanctions: CIDM, Kirin 9050, and Logic Folding

13 min · 10 Sep 2026

US sanctions bought time, not a lead. Huawei’s CIDM now ships Kirin 9050 with 1.5 µm wafer-to-wafer bonds — about 6× finer than TSMC SoIC. A coarse bond stacks two chips. A fine bond folds one circuit: two wafers, one netlist, one chip.

Notes: The Bottleneck Heuristic — Blackwell's Gauntlet, the ASIC Breakout, and the Optical Chokepoint (Pt.2)

Blackwell’s packaging, cooling, NVL72, and on-chip SFU bottlenecks exposed NVDA’s gauntlet — while Google’s AVGO-designed TPUv7 shattered the ASIC skepticism and the optical chokepoint tightened into 2025’s defining constraint.

21 min read 15 Apr 2026

18 min read 18 Mar 2026

SysMoore & Energy (Pt.3.3) - The Nuclear Investment Thesis

A three-decade “nuclear winter” of chronic underinvestment hollowed out the global uranium supply base — creating a structural scarcity shock as AI’s power hunger collides with a mining industry unable to respond at scale.

14 min read 03 Mar 2026

SysMoore & Energy (Pt.3.2) Reactor Design & Fuel

Industrialized modular SMR manufacturing is the only viable path to meet AI-driven nuclear demand — but advanced coolants, HALEU fuel, and TRISO fabrication bottlenecks will decide which designs (and which public companies) actually scale.

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