Two dies bonded face to face: transistors on the outside, wiring on the inside, and the hybrid-bond seam in between. Once that seam is as fine as the wires it joins, the stack routes like a single chip.

Huawei

Huawei After Sanctions: CIDM, Kirin 9050, and Logic Folding (Pt.2)

26 min · 18 Sep 2026

Cut off from EUV, Huawei is scaling a different way: folding two chips face to face so signals travel down rather than across. Part 2 explains why that raises clock speed without shrinking transistors, how the design repairs its own defects, and where the real wall lies.

Huawei After Sanctions: CIDM, Kirin 9050, and Logic Folding (Pt.1)

US sanctions bought time, not a lead. Huawei’s CIDM now ships Kirin 9050 with 1.5 µm wafer-to-wafer bonds — about 6× finer than TSMC SoIC. A coarse bond stacks two chips. A fine bond folds one circuit: two wafers, one netlist, one chip.

13 min read 10 Sep 2026

21 min read 15 Apr 2026

Notes: The Bottleneck Heuristic — Blackwell's Gauntlet, the ASIC Breakout, and the Optical Chokepoint (Pt.2)

Blackwell’s packaging, cooling, NVL72, and on-chip SFU bottlenecks exposed NVDA’s gauntlet — while Google’s AVGO-designed TPUv7 shattered the ASIC skepticism and the optical chokepoint tightened into 2025’s defining constraint.

18 min read 18 Mar 2026

SysMoore & Energy (Pt.3.3) - The Nuclear Investment Thesis

A three-decade “nuclear winter” of chronic underinvestment hollowed out the global uranium supply base — creating a structural scarcity shock as AI’s power hunger collides with a mining industry unable to respond at scale.

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