Layered memory hierarchies above the power infrastructure constraining AI infrastructure.

AI Bottlenecks

Notes: The Bottleneck Heuristic — The Memory Supercycle, Power Bottleneck, and Data Center Value Creation (Pt.3)

25 min · 29 Jun 2026

The memory supercycle is no longer just about HBM. Multi-tier architectures are pulling conventional DRAM and NAND into the same structural shortage, while power and PCB bottlenecks are now compounding the constraint.

Soitec - Where Silicon Photonics Begins

The near-monopoly on Photonics-SOI wafers that every leading silicon photonics foundry depends on as the starting material for AI’s optical interconnect boom.

27 min read 30 Apr 2026

13 min read 20 Apr 2026

Notes: POET Technologies - The Optical Interposer Thesis

POET’s Optical Interposer replaces costly active alignment with wafer-level pick-and-place packaging, opening AI optical engines to high-volume CMOS-scale manufacturing.

21 min read 15 Apr 2026

Notes: The Bottleneck Heuristic — Blackwell's Gauntlet, the ASIC Breakout, and the Optical Chokepoint (Pt.2)

Blackwell’s packaging, cooling, NVL72, and on-chip SFU bottlenecks exposed NVDA’s gauntlet — while Google’s AVGO-designed TPUv7 shattered the ASIC skepticism and the optical chokepoint tightened into 2025’s defining constraint.

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