Photonics: The $91 Billion Question (Pt.1)
CPO's $91 Billion Assumption, NPO's Quiet Momentum, and the OCS Wildcard — Mapping the Bottlenecks That Will Separate Winners from Consensus Darlings
NVIDIA
Soitec - Where Silicon Photonics Begins
The near-monopoly on Photonics-SOI wafers that every leading silicon photonics foundry depends on as the starting material for AI’s optical interconnect boom.
Notes: POET Technologies - The Optical Interposer Thesis
POET’s Optical Interposer replaces costly active alignment with wafer-level pick-and-place packaging, opening AI optical engines to high-volume CMOS-scale manufacturing.
Notes: The Bottleneck Heuristic — Blackwell's Gauntlet, the ASIC Breakout, and the Optical Chokepoint (Pt.2)
Blackwell’s packaging, cooling, NVL72, and on-chip SFU bottlenecks exposed NVDA’s gauntlet — while Google’s AVGO-designed TPUv7 shattered the ASIC skepticism and the optical chokepoint tightened into 2025’s defining constraint.
Notes: The Bottleneck Heuristic - Where Scarcity Meets Capability in the AI Value Chain (Pt.1)
The investment framework that separates signal from noise: where critical supply scarcity collides with AI’s exploding capability demand to create durable pricing power and mispriced opportunities across the value chain.
Notes: SiTime and the Rising Importance of Precision Timing in AI Systems
Summary
* Precision timing has shifted from commodity infrastructure to a system-level constraint in AI, and SiTime sits at a critical coordination layer as compute, networking, and interconnect complexity scale non-linearly.
* CED is the clear near-term growth engine, with MEMS-based timing content expanding across GPUs, NICs, switches,
Notes: Light is the Future (Pt.2)
Summary
* The optical supply chain bottleneck into 2026 is EML capacity, with 200G EMLs (needed for 1.6T) far tighter than 100G and keeping pricing and allocations elevated.
* Silicon photonics is the short-term “release valve” for EML shortages by shifting more functionality onto PICs and using CW light sources,