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Huawei After Sanctions: CIDM, Kirin 9050, and Logic Folding (Pt.2)
Huawei

Huawei After Sanctions: CIDM, Kirin 9050, and Logic Folding (Pt.2)

Cut off from EUV, Huawei is scaling a different way: folding two chips face to face so signals travel down rather than across. Part 2 explains why that raises clock speed without shrinking transistors, how the design repairs its own defects, and where the real wall lies.
26 min read 18 Sep 2026
Notes: ASM and the Rising Complexity of Chips & Why ALD Matters More Than Ever
ASM International
9 min read 08 Feb 2026

Notes: ASM and the Rising Complexity of Chips & Why ALD Matters More Than Ever

Summary * Semiconductor scaling is shifting from lithography alone to materials precision and 3D architectures, structurally increasing ALD intensity where ASM is strongest. * The transition to GAA, backside power delivery, and 2nm-class nodes creates a multi-year growth cycle driven by process complexity rather than wafer volume. * AI-driven demand
Themes - SysMoore & Hardware Renaissance In The Next Decade (Pt.2)
SysMoore
12 min read 04 Nov 2024

Themes - SysMoore & Hardware Renaissance In The Next Decade (Pt.2)

Summary * In Part 2 of the SysMoore series we compare the different approaches to chip-level packaging between Intel and AMD. * We also discuss PCBs, as scaling at the chip level reaches physical limits, PCBs are becoming essential for enabling high-speed, high-density connections necessary for advanced AI and
Themes - SysMoore & Hardware Renaissance In The Next Decade (Pt.1)
SysMoore
23 min read 25 Oct 2024

Themes - SysMoore & Hardware Renaissance In The Next Decade (Pt.1)

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