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Soitec - Where Silicon Photonics Begins
Summary
* Near-monopoly on Photonics-SOI, the engineered wafer every leading silicon photonics foundry depends on as starting material.
* Five compounding demand layers — cluster scale, optics-per-accelerator, SiPho share gains, scale-up optics, and memory disaggregation — all converging on the same wafer.
* SiPho is becoming the default, winning on cost and volume today and closing the performance gap with InP/EML at 1.6T and 3.2T.
* Pluggables → NPO → CPO is an intensification, not a subs
Notes: POET Technologies - The Optical Interposer Thesis
Summary
* We plan to add a lot more coverage on the optical networking supply chain in the coming weeks. If you would like a complimentary call to discuss in advance, please contact service@convequity.com.
* POET's Optical Interposer replaces costly active alignment with passive, wafer-level pick-and-place assembly, turning
Notes: The Bottleneck Heuristic — Blackwell's Gauntlet, the ASIC Breakout, and the Optical Chokepoint (Pt.2)
Summary
* Following Part 1's investment heuristics, Part 2 recaps the pivotal developments of 2024–25, starting with NVDA's Blackwell — delayed ~9–12 months by packaging respins, liquid-cooling redesigns, NVL72 reliability issues, and an on-chip SFU bottleneck.
* Google's TPUv7 (AVGO-designed) shattered the "ASICs can&