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Huawei After Sanctions: CIDM, Kirin 9050, and Logic Folding
US sanctions bought time, not a lead. Huawei’s CIDM now ships Kirin 9050 with 1.5 µm wafer-to-wafer bonds — about 6× finer than TSMC SoIC. A coarse bond stacks two chips. A fine bond folds one circuit: two wafers, one netlist, one chip.
Notes: The Bottleneck Heuristic — The Memory Supercycle, Power Bottleneck, and Data Center Value Creation (Pt.3)
The memory supercycle is no longer just about HBM. Multi-tier architectures are pulling conventional DRAM and NAND into the same structural shortage, while power and PCB bottlenecks are now compounding the constraint.
Notes: ASM and the Rising Complexity of Chips & Why ALD Matters More Than Ever
Summary
* Semiconductor scaling is shifting from lithography alone to materials precision and 3D architectures, structurally increasing ALD intensity where ASM is strongest.
* The transition to GAA, backside power delivery, and 2nm-class nodes creates a multi-year growth cycle driven by process complexity rather than wafer volume.
* AI-driven demand