Notes: Huawei’s 910C and CM384: A Strategic Shock to the NVIDIA Thesis (Pt.1)

Summary

• Huawei’s 910C and CM384 achieve H100-class and Blackwell-scale performance using older nodes, challenging the idea that leading-edge silicon is NVIDIA’s unassailable moat.
• System-level innovations and full-stack integration enable Huawei to deliver better real-world efficiency and scalability in key AI workloads.
• While uninvestable, Huawei’s rise threatens NVIDIA’s pricing power and dominance in China and may erode global competitive differentiation over time.

Executive Summary

• The DeepSeek moment is coming for AI hardware. We believe Huawei's Ascend 910C marks a turning point—akin to DeepSeek V2's quiet breakthrough before V3 and R1 reached mass recognition. It signals the beginning of a shift where system-level innovation, not just raw silicon, defines leadership.
• Following a pause in 2022, Huawei revived its Ascend chip program amid rising AI demand and U.S. sanctions. The result: the 910C and CM384 — credible Hopper-class and Blackwell-scale alternatives — built on mature 7nm and HBM2e, but architecturally scaled to deliver 2x the system performance of NVIDIA’s flagship.
• While the 910C’s chip-level performance is comparable to the H100, Huawei’s deep integration across networking, memory, power, and software enables it to exceed real-world performance benchmarks, including inference throughput and system linearity, even on older nodes.
• Huawei is not just matching competitors — it is leapfrogging them through a vertically integrated strategy that prioritizes architectural ingenuity over leading-edge fabs. This mirrors its contrarian success in LiDAR-based ADAS, where it reduced costs 10x to deliver highway L3 autonomy ahead of Tesla.
• Huawei Cloud is emerging as a challenger to the top three hyperscalers, underpinned by a broad portfolio of in-house products and early deployment of AI-native security agents. Its Palantir-style forward-deployed engineering model further enhances adoption and AI ROI.
• Huawei’s rapid catch-up in AI compute—achieving H100-level performance and Blackwell-level system throughput using older nodes—challenges the assumption that NVIDIA’s moat is protected by cutting-edge silicon alone.
• While Huawei is not investable, its rise erodes NVIDIA’s long-term pricing power and system differentiation, especially in China and other non-Western markets where Huawei can offer comparable or superior performance at lower cost—undermining the exclusivity that underpins the NVIDIA bull case.

The most ironic outcome often becomes the most likely. U.S. sanctions on Huawei and the broader Chinese semiconductor ecosystem are increasingly showing signs of backfiring. Growing evidence suggests that these restrictions, intended to suppress China’s chip advancement, are instead accelerating the development of its domestic semiconductor industry. While the sanctions have caused short-term disruption, they are now laying the groundwork for long-term resilience and technological independence.

At the Huawei Cloud Ecosystem Conference on April 10, 2025, Huawei officially unveiled the Ascend 910C and Cloud Matrix 384 — validating predictions we made during our NVDA MSU report in December 2023. Similar in concept to NVIDIA’s Blackwell, the 910C packages two 910B dies together, while keeping the underlying microarchitecture largely unchanged.

The 910B itself marked the revival of Huawei’s Ascend 910 AI chip program, which had been severely disrupted by U.S. sanctions beginning in 2019. It was essentially a reissue of the original 2019 Ascend 910, designed to rival NVIDIA’s A100. The newly launched 910C builds on this by combining two 910B dies into a single package, without changes to the microarchitecture. It still relies on SMIC’s 7nm node and HBM2e memory, resulting in only marginal performance gains at the chip level. However, Huawei’s packaging strategy closely parallels NVIDIA’s approach with Blackwell, which also combines two dies and retains the Hopper microarchitecture. The difference is that Blackwell advances further with next-gen HBM3e memory and rebalanced core allocation — offering more meaningful performance improvements than Huawei’s iteration.

910C & CM384 - System Edge As Expected

910C = H100

NPU has better compute efficiency vs. GPGPU

Beyond modest gains in FP16 performance and the use of a dual-die NPU package, the 910C’s most notable advancement is its significantly enhanced scale-up interconnect, delivering 2.8 Tbps of uni-directional bandwidth per chip (shown as 2,800 Gb/s uni-di in the table). For comparison, NVIDIA’s Blackwell (GB200) achieves 7.2 Tbps uni-directional bandwidth per chip (shown as 7,200 Gb/s uni-di in the table), over 2.5x higher. That said, Blackwell isn’t an entirely direct comparison — Huawei’s 910C is more accurately positioned against NVIDIA’s H100 or H200. Relative to the H100, the 910C is built using an older process node and HBM memory generation. However, by leveraging a chiplet-based architecture, the 910C delivers 75% of the H100’s FP16 throughput, 1.6x the memory capacity, and operates at 1.14x the power consumption.

More interestingly, Huawei claims that in its real-world tests, the 910C is able to deliver 1920 tokens per second (TPS) in DeepSeek V3 single-card decoding, while the H100 achieves only 1850 TPS. Thanks to deep operator and software stack optimization, Huawei is able to deliver better inference results despite lower raw compute. This is plausible, in our view, because the 910C is not a GPGPU burdened with technical debt and general-purpose design compromises. Instead, the 910C is an AI-native Neural Processing Unit, purpose-built and optimized exclusively for AI workloads, similar to other AI chips like Tenstorrent, Tranium, and TPU. Like these, Huawei integrates custom CPU cores within the NPU to enhance flexibility for tasks like scheduling. In contrast, with NVDA chips, DeepSeek must build its own scheduler and allocate 20% of H800 cores for this function.

It is also notable that Huawei achieved this performance through collaboration with SiliconFlow, an inference framework startup. Huawei delivered 1920 TPS for single-card decoding throughput under a single-user 20 TPS rate limit, which outpaces the H100’s 1850 TPS. Huawei is not merely playing the numbers game by maximizing throughput at the expense of per-user performance. Looking ahead, Huawei plans to achieve 4000 TPS, which, if realized, would represent another major shock to NVDA.

Additionally, it appears that deeper hardware-software integration and the NPU’s native flexibility allow Huawei to achieve a 20% reduction in long-sequence inference latency — a critical metric for future tasks like agents, retrieval-augmented generation (RAG), and advanced reasoning workloads.

Chip Design Excellence Despite Process Constraints

Huawei has delivered a credible alternative to NVIDIA’s H100—matching or exceeding several metrics — despite relying on less advanced process nodes and memory. The larger die size of the 910C is not due to design inefficiencies but rather the lack of access to cutting-edge logic nodes and HBM memory. This pattern isn’t unique to Huawei; Broadcom (AVGO), a key networking peer, has developed the TPUv7p (check our post on X), which surpasses NVIDIA’s GB200 on key PPAC (performance, power, area, cost) metrics. The TPUv7p, expected to ship in late 2025, benefits from TSMC’s N3 process, which offers a 30% density gain and 15% performance uplift over the N4 node used in Blackwell. Even without process node advantages, AVGO’s chip design — especially its power efficiency and area optimization — outperforms Blackwell, aided by ahead-of-time software compilation and advanced networking IP that are both smaller and more efficient than rivals.

Similarly, the 910C demonstrates strong area efficiency. It offers slightly better real-world performance than the H100 today, with a projected 2x improvement over the H100 in future iterations. Although its die area is 1.6x larger than the H100, this is largely due to process limitations. If Huawei had access to TSMC’s N4 node, the die size would shrink to just 1.14x that of the H100, based on density differences between SMIC 7nm and TSMC N4. Power consumption is also comparable — remarkable given that SMIC’s 7nm typically consumes 30% more power than TSMC’s N4/5. From a pure chip design standpoint, Huawei is approaching or even exceeding NVIDIA, especially considering that a portion of the 910C’s area is allocated to chiplet integration and HBM interconnects. The overall PPAC is highly impressive given Huawei’s constraints around process technology and memory availability.

Furthermore, Huawei accomplished all this despite the Ascend project being nearly halted between 2019 and 2023. Ascend was once a low-priority initiative and did not see much success when the 910A launched in 2019. It was not until November 2022 and the first half of 2023, amid rising demand for AI chips and stricter US sanctions, that Huawei fully recognized the strategic importance of the Ascend NPU.

CM384 = GB200x2

As anticipated, by interconnecting more chips at scale, Huawei is leveraging Ampere-era process nodes and memory to reach Hopper-class chip performance, ultimately achieving 1.67x the system-level BF16 throughput of Blackwell (910C CM384 at 300 PFLOPS vs. GB200 NVL72 at 180 PFLOPS). The CM384 further strengthens Huawei’s competitive position through system-level architectural innovations. While NVIDIA’s Blackwell system caps its scale-up domain at 72 GPUs per rack, Huawei unifies up to 384 910C chips in a single scale-up domain — a 5.33x increase — by linking 16 racks (12 NPU racks and 4 network switching racks), enabling these chips to operate as if on a single server. This architecture also delivers 2.13x the total memory bandwidth and 3.57x the total memory capacity compared to GB200 NVL72, albeit at 3.86x higher system power. Despite higher absolute power draw, Huawei’s CM384 shows clear scaling advantages in bandwidth, capacity, and interconnect performance, facilitated by over 6,900 400G optical modules and 3,168 fiber cables, as noted in the system buildout.

Fiber vs. Copper = LiDAR vs. Pure Camera

Huawei’s ability to scale up to 384 interconnected NPUs in a single compute domain hinges on its deep expertise in networking and its strategic embrace of all-optical (fiber-based) interconnects. While this approach increases system cost and power, Huawei sees it as a worthwhile trade-off for the performance, flexibility, and reliability gains it enables.

By contrast, NVIDIA confines its scale-up domain to a single rack (72 GPUs), prioritizing density, cost control, and reliability. Its NVLink-based architecture relies on copper cabling, which is cheaper but limited in reach and scalability. Part of this conservatism stems from past challenges: NVIDIA reportedly failed to bring its all-optical NVL256 Grace-Hopper prototype to production due to reliability issues stemming from managing vast numbers of transceivers. Huawei, meanwhile, has long designed and produced optical modules in-house, giving it both technological control and cost-reduction leverage in ways NVIDIA cannot match.

Optical Scale-Out at Data Center Scale

Despite the higher cost and power consumption of fiber, Huawei’s Cloud Matrix CM384 system benefits from several practical advantages:

• Longer optical reach simplifies rack-to-rack integration and lowers infrastructure complexity.
• A 50kW Huawei rack is easier to deploy and can even be air-cooled, whereas NVIDIA’s 145kW NVL72 racks require more aggressive cooling and power infrastructure.
• Huawei’s willingness to push into more complex territory is unlocking real differentiation at scale — performance, deployment simplicity, and vertical cost control.

The LiDAR Analogy: Betting on the Complex but Scalable Path

This divergence echoes the LiDAR vs. pure camera debate in autonomous driving. Just as Elon Musk dismissed LiDAR as too expensive and unnecessary — insisting Tesla would succeed with camera-only ADAS — Jensen Huang has resisted optical modules in data center scaling due to concerns around cost and complexity.

Huawei challenged this thinking in both domains:

• In ADAS, it invested heavily in in-house LiDAR development and manufacturing.
• Its upcoming ADS4 Ultra system, set to launch in 2H 2025, uses a mix of one high-power long-range LiDAR and three short-range LiDARs (left, right, rear) to enable the world’s first commercial L3 autonomous highway driving system.
• Meanwhile, Tesla’s vision-only L3 system is still in development, and Huawei’s solution may arrive first — with greater safety and technical robustness.

Commoditizing Complexity: Huawei’s Playbook

Huawei’s ability to vertically integrate and commoditize complex hardware—whether LiDAR or optical modules—gives it an edge. By driving LiDAR costs below $200, Huawei disproved Musk’s claims. Now, it's applying the same model to optical modules, an area where Chinese firms excel at scaling manufacturing and squeezing costs.

Unlike advanced semiconductors, optical modules don’t require EUV lithography, making them much easier to produce domestically at scale. Huawei’s goal is to manufacture domestic fiber interconnects and optical modules so cheaply that even with tariffs, they undercut NVIDIA’s U.S. supply chain.

Actual performance and power efficiency is better than expected

Examining raw compute power, CM384, with 5.3x as many chips, delivers only 1.67x more compute. This comes at the expense of requiring significantly more networking hardware, resulting in 2.3x the power consumption per BF16 FLOPS. However, CM384 provides 3.57x more memory capacity while maintaining memory power efficiency close to NVL72, at 1.09x. This aligns with our view that memory is becoming more commoditized compared to compute, and reinforces our criticism of the US government's recent ban on H20 sales — highlighting that sanctioning memory rather than compute is an ineffective strategy.

Looking deeper into performance metrics, it is impressive that Huawei achieves a 55% MFU (Model FLOPS Utilization) versus NVIDIA’s 43%. In practice, this means the CM384 can deliver 300 x 0.55 = 165 PFLOPS, compared to NVL72’s 180 x 0.43 = 77.4 PFLOPS. When considering MFU-discounted BF16 FLOPS, the CM384 actually offers 2.13x the performance of NVL72. This is likely thanks to the use of all optical modules, NPU-native control flow, and networking optimization.

Huawei also claims an impressive 99% linearity in clusters exceeding 10,000 cards, significantly outperforming NVIDIA’s 95%. To put this in perspective: for a 100,000-GPU cluster running continuously for 3 months, this 4% difference in linearity is substantial.

Calculation:

1. Basic Parameters

• Number of GPUs: N = 100,000
• Period: T = 3 months = 90 days = 2,160 hours
• Total workload: 100,000 GPUs × 2,160 hours = 216,000,000 GPU-hours

2. Resource Consumption Calculation

99% Parallel Efficiency

•  Total GPU-hours = 216,000,000 / 0.99 ≈ 218,181,818

95% Parallel Efficiency

•  Total GPU-hours = 216,000,000 / 0.95 ≈ 227,368,421

Difference

•  227,368,421 - 218,181,818 = 9,186,603 GPU-hours

So, for three months of continuous computation on 100,000 GPUs, reducing parallel efficiency from 99% to 95% results in approximately 9,187,000 wasted GPU-hours. Assuming a cost of $4 per GPU-hour, a 4% decrease in linearity could translate to a $36m increase in actual training costs.

Lastly, for end-system power, we reference SemiAnalysis’ estimate of 559 kW for the CM384, or 3.8x the power consumption of NVL72. This is based on their assumption that each 400G optical module transmits data over 8 lanes at 50 Gb/s, resulting in 2,800 Gb/s of total scale-up bandwidth per chip (7 modules x 8 lanes x 50 Gb/s). However, in high-end implementations, those lanes can run faster. A premium QSFP-DD module (the industry-standard hardware form factor for high-speed optical and copper transceivers) can support 8 lanes at 53–56 Gb/s, reaching 424–448 Gb/s total per module. And if Huawei controls the full stack — chip, fiber, and protocol — it could push this even further, up to 8×64 Gb/s or more. Unlike NVIDIA, which must conform to Dell or Foxconn rack standards, Huawei can optimize its fiber speeds more aggressively. In practice, CM384’s actual power draw could be below 500 kW, bringing it closer to 3.5x the NVL72’s power while delivering 2x the performance — meaning its power consumption per unit of performance is only 1.75x higher.

System edge

Huawei also claims it can support over 40 days of uninterrupted training — significantly longer than NVIDIA’s 26 days. One of the biggest pain points and technical barriers for 10,000+ GPU clusters isn’t just linking chips together, but ensuring that such a massive fleet of all-to-all-connected processors can operate 24/7 for months at a time. During the training phase, even a tiny 0.01% failure in just one chip can bring down the entire system. Even today, only a handful of companies worldwide can successfully manage long-duration training on 10,000+ NVIDIA GPUs, let alone the 100,000+ scale expected in the near future. NVIDIA is well aware of this challenge — which is why it builds and operates its own large clusters, “dogfooding” not only the chip but the entire system to ensure reliability.

Compared to NVIDIA, Huawei holds several major advantages:

• Deep Networking Roots: With decades of experience serving telcos, Huawei is accustomed to systems where extremely high uptime and rapid issue resolution are mandatory, whether through automation, manual methods, templates, or technical services.
• Talented Workforce: Huawei commands a vast pool of highly skilled talent, distinguished by sharp execution and strong vision.
• Comprehensive Product Portfolio: Huawei operates across the entire vertical and horizontal stack — from wafer fabrication equipment (WFE) and chip design to data center infrastructure, cloud services, and end applications, including consumer devices and vehicles.

These strengths allow Huawei to scale further than NVIDIA, controlling the costs of all-optical, liquid-cooled racks, ensuring robust power supply, labor force, and predictive maintenance. With both superior workforce quantity and quality, Huawei can afford to build and maintain such large-scale systems, keeping the CM384 competitive and reliable. Scaling up single nodes and scaling out large clusters remains a greenfield for engineering, requiring continuous innovation to resolve new challenges as they arise. In fact, this systemic reliability is part of NVIDIA’s moat beyond CUDA.

Even if AMD manages to improve ROCm, without a reliable, scalable cluster solution with high MFU, low mean time between failures (MTBF), and straightforward maintenance, selling cheaper chips will not guarantee a lower TCO. This makes Huawei’s ambition to outpace NVIDIA on every front even more impressive: from operator optimization on par with, or even surpassing CUDA, to efficient inference frameworks, to robust and reliable cluster management, to providing AI PaaS cloud and vertical-specific AI services (like Palantir), and training trillion-parameter foundation models and state-of-the-art ADAS models rivaling Tesla.

According to Huawei, before launching the 910C and CM384, they successfully deployed a 128,000-GPU cluster with CM384 and trained a MoE (Miixture of Experts) transformer ADAS model that is now ready for highway L3 applications, soon to be available in Huawei’s own ADAS system.

A particularly impressive aspect of Huawei is its ability to maintain “day 1” energy and innovation regardless of its massive revenue and scale. While most companies lose their edge as they grow and diversify, Huawei consistently maintains leadership across numerous domains and delivers a competitive edge by leveraging synergies across its broad range of businesses.

For example, unlike AMD — which has historically been confined to single-card performance and is now only gradually improving in single-node performance — Huawei recognized as early as 2023 that the industry was shifting from single-node compute to a new era defined by the interplay of compute x networking x memory x electricity. By scaling across all four dimensions simultaneously, Huawei has succeeded in driving rapid system-level performance improvements.

Huawei also has a very advanced R&D and academic research team for cutting edge trends like P/D (Prefill/Decode) inference clusters. In its latest publication, Huawei claims to deliver a 1.6x gain via solving the drawbacks of NVDA's inferencing system Dynamo and improve the overall system utilization further. For a quick recap, there are two phases for each request: a compute-intensive Prefill stage for context processing, and a memory-intensive Decode stage for token generation. To prevent performance interference between these stages, existing LLM service systems often use a Prefill-Decode (PD) separation deployment strategy, assigning each stage to different machines. However, this leads to significant GPU resource waste — Prefill instances exhibit low memory utilization, while Decode instances underutilize compute resources.

To solve this, advanced solutions like Adrenaline have emerged. Adrenaline introduces an attention separation and offloading mechanism, specifically designed to enhance LLM inference system resource utilization and performance. The core idea is to separate a portion of the attention computation from the Decode stage and offload it to Prefill instances. Given that decode attention is highly memory-intensive, Adrenaline increases the memory capacity and bandwidth utilization on Prefill instances, while also enabling larger batch sizes for the Decode stage, thereby boosting compute utilization. Together, these optimizations improve end-to-end inference throughput.

Adrenaline achieves this with three key technologies: load-aware offloading scheduling, low-latency decode synchronization, and resource-efficient Prefill colocation. Experimental results show that, compared to state-of-the-art PD-separated inference systems, Adrenaline improves Prefill memory capacity utilization, memory bandwidth utilization, and Decode compute utilization by up to 2.3x, 2.07x, and 1.67x respectively, and increases Decode throughput by 1.68x.

This kind of innovation in inference resource scheduling and optimization is directly reflected in Huawei Cloud’s service stack, where dynamic allocation and elastic inference services can deliver significant efficiency gains for large-scale LLM deployments. It exemplifies how Huawei’s technical approach combines both hardware and software-level advances to maximize performance and cost-effectiveness, reinforcing its leading position in the AI and cloud ecosystem.

Taking its competitive advantage a step further, Huawei is also optimizing the cloud service layer on top of the system layer — a topic we will explore in more detail later.